It has been a recent trend in dynamic random access memory (DRAM) to increase the density of DRAM integrated circuits. However, as higher density DRAM cells are developed, the area available for capacitors that are used in the DRAM cells decreases. In order to decrease the area of capacitors while maintaining reliability standards, it is important to be able to maintain the capacitance of each capacitor while decreasing its footprint. Recently, capacitors having a three-dimensional structure have been suggested to increase cell capacitance. Such capacitors include, for example, double-stacked, fin-structured, cylindrical, spread-stacked, and box structured capacitors.
There is also a challenge to develop methods of manufacturing these capacitors that minimize the manufacturing costs and provide maximum process tolerance to maximize product yields. In one standard capacitor under bit line (CUB) process, a storage node contact is formed to connect to a landing pad. As is known in the art, a landing pad is frequently used for below submicron technology to reduce cell size. For example, Samsung Corp. of South Korea uses landing pad technology extensively. This is followed by formation of a storage node, deposition of oxide-nitride-oxide (ONO) and then formation of a capacitor top plate. This prior art process requires three photoresist masks to complete a DRAM capacitor, namely the photoresist masks used in forming the storage node contact, the storage node, and the capacitor top plate. Then, capacitor planarization is performed, and a bit line contact and a bit line are formed. As a result of the large step height of the storage node, which is typically about 4000 to 7000 angstroms, good planarization is difficult to achieve.
The present invention is directed to a method for forming a fin-trench structured DRAM capacitor and is preferably to be used in capacitor under bitline process. The present method reduces one photoresist mask layer and eliminates the capacitor planarization concern, while increasing capacitor area. Thus, the present method minimizes the manufacturing costs and provides maximum process tolerance to maximize product yields.